In testing semiconductor devices such as ICs and LSIs by a semiconductor test system, a semiconductor IC device to be tested is provided with test signals (test patterns) produced by a pattern generator in the semiconductor test system at its appropriate test pins at predetermined test timings. The semiconductor test system receives output signals from the IC device under test in response to the test signals. The output signals are strobed (sampled) by strobe signals at predetermined timings to be compared with expected output data to determine whether the IC device functions correctly or not.
In the case where the device under test (DUT) is a semiconductor memory, the test pattern applied to the DUT consists of address data, write data, and control data. After writing predetermined data in predetermined addresses (memory cells) of the DUT, the data in the addresses is read to determine whether the stored data in the memory is the same as the write data. For testing a semiconductor memory, a test pattern generated by the pattern generator includes various data and control signals including the address data, write data and control data noted above as well as expected data, address and control data for storing test results in a failure memory, and etc.
An example of basic structure in a typical semiconductor test system having a pattern generator is shown in FIG. 1. Within the context of the invention, the pattern generator can be applied to a semiconductor test system which is exclusively configured for testing semiconductor memories as well as to a semiconductor test system configured for testing an LSI such as a system-on-a-chip IC having a memory block or memory core therein as apart of the LSI.
In FIG. 1, the semiconductor test system includes a timing generator TG for generating timing clocks, a pattern generator PG for generating test pattern including various address data and control signals, a format controller (wave formatter) FC for wave formatting the test pattern, a pin electronics for interfacing with a device under test (DUT), a digital (logic) comparator DC for comparing an output of DUT with expected data, and a failure memory FM including an address fail memory AFM for storing test results for failure analysis.
Based on timing clocks from the timing generator TG, the pattern generator PG generates test patterns such as address data and control signals which are supplied to the format controller FC. The format controller FC provides the test pattern to the DUT with specified waveforms and timings through the pin electronics. The pattern generator PG also generates expected data EXP which is supplied to the digital comparator DC to compare with the data from the DUT at the timings of strobe signals from the timing generator TG.
Upon detecting a mismatch between the DUT output data and the expected data EXP, an error indication is produced by the comparator DC. Such error (failure) data is stored in the failure memory FM (or address fail memory AFM therein) in the addresses specified by the address data from the pattern generator PG corresponding to the addresses of the DUT. The error data in the failure memory FM could represent the actual value of the device output pin at the strobe point, or it could be just a single bit indicating pass or fail. The test engineers and design engineers use the error data in the failure memory FM to analyze correctness of the device design and functions.
As is well known in the art, a memory is configured by a large number of memory cells each being specified by a combination of a row (X) address and a column (Y) address. In memory testing, one of the important test items is to examine whether there is an interference between memory cells, which is sometimes called “pattern sensitive faults” or “neighborhood pattern sensitive faults”. Typically, such a fault is examined by writing data (such as “1”) in a particular memory cell which is opposite to data (such as “0”) in adjacent memory cells. The semiconductor test system monitors whether the particular cell correctly stores the write data “1” when all the neighborhood cells store the write data “0”
In other words, a pattern generator in the semiconductor test system is designed to include a functionality dedicated to memory testing which is able to invert write data for a specified memory cell (address) of the memory device under test. Because of such a data inversion function provided in the pattern generator, a complicated test pattern can be generated at high speed without requiring a complicated test program.
A pattern generator PG used for such memory testing is usually an ALPG (Algorithmic Pattern Generator) having an arithmetic function therein for generating test patterns including address data, write data, and control data to be applied to the DUT. More specifically, the pattern generator generates test patterns to be applied to the DUT pins such as an address pin, data pin, and control pin. An example of the control data includes chip enable (CE). write enable (WE), output enable (OE), row address strobe (RAS) and column address strobe (CAS). The pattern generator PG also generates expected pattern EXP to be provided to the digital comparator DC for comparison with the data read from the DUT, and address data and control data for controlling the address fail memory AFM for storing the test results therein. The pattern generator PG further generates control signals such as an inversion request signal, which is the subject of the present invention as will be described in detail later.
FIG. 2A shows a block diagram showing an essential structure of the pattern generator PG. In this example, the pattern generator is comprised of a sequence controller 400, an address generator 200, a data generator 300, and a control signal generator 100. As shown in FIG. 1, the pattern generator receives the timing (reference) clocks from the timing generator TG, thereby generating the test pattern (address data, write data, and control data, etc.) in synchronism with the reference clock.
The address generator 200 generates address data 200s, the data generator 300 generates data 300s, and control signal generator 100 generates control signals 100s. The data 300s includes an inversion request signal 110s which is now explained in detail. The inversion request signal 110s (FIG. 2B) is to produce a test pattern which can detect the “pattern sensitive faults” or “neighborhood pattern sensitive faults” of the memory device under test as mentioned above.
The inversion request signal 100s is to produce write data such as “1” for a specified memory cell when the write data for all other neighboring memory cells is “0”, or vice versa. Typically, a location of such a specified memory cell is shifted in a diagonal direction such as shown by hatched portions of FIG. 4 to effectively detect “pattern sensitive faults”. For performing such a test, the pattern generator PG generates the address data which increments by one to sequentially access the memory cells, and write data such as “0” for all of the memory cells, and an inversion request signal for a specified memory cell to invert the write data to “1”.
FIG. 2B is a block diagram showing essential components in the pattern generator related to generating the inversion request signal 110s. It should be noted that this example is an internal knowledge of the inventor and assignee of this invention, but not publicly available information. Therefore, the example of FIG. 2B is not prior art against the present invention. In the example of FIG. 2B, the number of X address lines and Y address lines is 16, respectively. The inversion request signal circuit of FIG. 2B includes a diagonal inversion set register 10, an accumulator 20, an X AND gate 32, a Y AND gate 34, and a comparator (exclusive OR) 40.
The diagonal inversion set register 10 is a register with a 16-bit width for storing a set value specifying which diagonal line to be selected as locations of specific memory cells for data inversion. The accumulator 20 is a 16-bit arithmetic adder which receives the Y address data with a 16-bit width from address generator 200 as well as the set value from the diagonal inversion set register 10, and outputs the added result of 16-bit data YA. During this process, a carry over signal resulted from the addition is not used.
The X AND gate 32 is provided with the maximum X address value at one input while X address data is provided at another input. The Y AND gate 34 is provided with the maximum Y address value at one input while the added result YA from the accumulator 20 is provided at another input. The maximum X address value and maximum Y address value are provided as mask data for limiting an effective bit width in the 16-bit width of the address data based on the size of the DUT. For example, in the memory configuration shown in FIG. 3, because the effective bit width is 2-bit, the mask data (maximum address value) expressed in a binary form is “0000,0000,0000,0011”, thereby masking data bits higher than the first two bits.
The Y AND gate 34 produces a 16-bit output data YB resulted from logic AND for each bit between the maximum Y address value and the accumulated output 16-bit data YA. The output data YB (Y comparison data) is provided to the comparator 40. The X AND gate 32 produces a 16-bit output data XA resulted from logic AND for each bit between the maximum X address value and the 16-bit width X address data. The output data XA (X comparison data) is provided to the comparator 40.
The comparator 40 receives the 16-bit width Y comparison data YB and the 16-bit width X comparison data XA, compares each and every corresponding bit therebetween, and generates an inversion request signal only when all of the bits matched with one another. As a result of this process, the write data for specified memory cells in the DUT is automatically inverted and written therein. In addition, the expected data provided to the digital comparator DC is also inverted accordingly so that the logic comparison with the read out data of the DUT can be conducted correctly. The information on the data inversion is provided to the address fail memory AFM as well to be used for failure analysis.
Therefore, by defining a set value in the diagonal inversion set register 10 and other data such as maximum address data, the inversion request signal 110s noted above can be generated. Thus, data inversion is performed for memory cells on an arbitrary diagonal line on an array of memory cells without requiring to produce a complicated pattern program.
The logic operation performed in the block diagram of FIG. 2B for generating the inversion request signal 110s is summarized in the conditional equation 1 below.(Y address of memory cell+diagonal inversion set value) AND maximum Y address value=X address of memory cell AND maximum X address value  Conditional equation 1:
FIG. 3A shows an example of relationship between the neighborhood memory cells and the specified memory cells in a diagonally line for writing inverted data therein. In this example, the set value in the diagonal inversion set register 10 is “#3” and the memory cells on the specified diagonal line are denoted by “#3”.
Further, conditional equation 2 below is to reverse the data on the backward diagonal line perpendicular to the diagonal line defined by the conditional equation 1.*(Y address of memory cell+diagonal inversion set value) AND maximum Y address value=maximum X address value AND Y address of memory cell  Conditional equation 2:
Here, a mark * at the front of the equation 2 signifies bit inversion which inverts the data indicating the added result within the parentheses that comes immediately after the mark. The relationship between the neighborhood memory cells and specified memory cells in the reverse diagonally line for writing inverted data therein is shown in FIG. 3B. In this example, the set value in the diagonal inversion set register 10 is “#3” and the memory cells on the specified diagonal line are denoted by “#3”. The diagonal line of FIG. 3B is perpendicular to the diagonal line of FIG. 3A.
A specific example of diagonal inversion operation is described hereafter based on the circuit diagram of FIG. 2B for generating the inversion request signal 110s. For the simplicity of explanation, the following description is made for the case where the memory device under test has an array of 4×4 memory cell as shown in FIG. 4. In this procedure, the write data for specified memory cells on a diagonal line on the memory cell array is inverted. Since the memory cells are arranged in a “4×4” array, the maximum value of X address and Y address is “#3”, respectively. It is assumed that both of the X address and Y address start from “#0”, and the set value for the diagonal inversion set register 10 is “#3”. Thus, only the lower two bits are considered in the following process by masking third or higher bits.
Based on the conditions mentioned above, the process of determining whether the write data for a memory cell defined by the address data should be inverted is described in the following for each and every X, Y address. This process is conducted by computing the right and left sides of the conditional equation 1 above, and when the computed results match with each other, it is determined that the write data for the address is inverted.
First, when the address of a memory cell is (X, Y)=(0, 0), the conditional equation of left side “(Y address of memory cell+diagonal inversion set value) AND maximum Y address value” is (0+3) AND 3=3, and the conditional equation of right side “(X address of memory cell AND maximum X address value)” is 0 AND 3=0, thus, left side≠right side. Therefore, the data is not inverted for the memory cell. Note that “0+3” above is “00+11” which is “11” in binary form, thus “(0+3) AND 3” above is “11 AND 11” which is “11” in binary form, i.e., “3”. Also note that “0 AND 3” above is “00 AND 11” which is “00” in binary form, i.e., “0”. Similar rule applies to the following descriptions.
Second, when the address of the next memory cell is (x, Y)=(1, 0), the conditional equation of left side “(Y address of memory cell+diagonal inversion set value) AND maximum Y address value” is (0+3) AND 3=3, and the conditional equation of right side “(X address of memory cell AND maximum X address value)” is 1 AND 3=1, thus, left side≠right side. Therefore, the data is not inverted for this memory cell.
Third, when the address of a memory cell is (X, Y)=(2, 0), the conditional equation of left side “(Y address of memory cell+diagonal inversion set value) AND maximum Y address value” is (0+3) AND 3=3, and the conditional equation of right side “(X address of memory cell AND maximum X address value)” is 2 AND 3=2, thus, left side≠right side. Therefore, the data is not inverted for the memory cell.
Fourth, when the address of a memory cell is (X, Y)=(3, 0), the conditional equation of left side “(Y address of memory cell+diagonal inversion set value) AND maximum Y address value” is (0+3) AND 3=3, and the conditional equation of right side “(X address of memory cell AND maximum X address value)” is 3 AND 3=3, thus, left side=right side. Therefore, the data is inverted for this memory cell.
Fifth, when the address of a memory cell is (X, Y)=(0, 1), the conditional equation of left side “(Y address of memory cell+diagonal inversion set value) AND maximum Y address value” is (1+3) AND 3=0, and the conditional equation of right side “(X address of memory cell AND maximum X address value)” is 0 AND 3=0, thus, left side=right side. Therefore, the data is inverted for this memory cell. Note that “1+3” above is “01+11” which is “100” in binary form, and only lower two bits are valid by masking the higher bits, thus “(1+3) AND 3” above is “00 AND 11” which is “00” in binary form, i.e., “0”. Similar rule applies to the following descriptions.
Sixth, when the address of a memory cell is (X, Y)=(1, 1), the conditional equation of left side “(Y address of memory cell+diagonal inversion set value) AND maximum Y address value” is (1+3) AND 3=0, and the conditional equation of right side “(X address of memory cell AND maximum X address value)” is 1 AND 3=1, thus, left side≠right side. Therefore, the data is not inverted for the memory cell.
Seventh, when the address of a memory cell is (X, Y)=(2, 1), the conditional equation of left side “(Y address of memory cell+diagonal inversion set value) AND maximum Y address value” is (1+3) AND 3=0, and the conditional equation of right side “(X address of memory cell AND maximum X address value)” is 2 AND 3=2, thus, left side≠right side. Therefore, the data is not inverted for this memory cell.
Eighth, when the address of a memory cell is (X, Y)=(3, 1), the conditional equation of left side “(Y address of memory cell+diagonal inversion set value) AND maximum Y address value” is (1+3) AND 3=0, and the conditional equation of right side “(X address of memory cell AND maximum X address value)” is 3 AND 3=3, thus, left side≠right side. Therefore, the data is not inverted for the memory cell.
Ninth, when the address of a memory cell is (X, Y)=(0, 2), the conditional equation of left side “(Y address of memory cell+diagonal inversion set value) AND maximum Y address value” is (2+3) AND 3=1, and the conditional equation of right side “(X address of memory cell AND maximum X address value)” is 0 AND 3=0, thus, left side≠right side. Therefore, the data is not inverted for this memory cell.
Tenth, when the address of a memory cell is (X, Y)=(1, 2), the conditional equation of left side “(Y address of memory cell+diagonal inversion set value) AND maximum Y address value” is (2+3) AND 3=1, and the conditional equation of right side “(X address of memory cell AND maximum X address value)” is 1 AND 3=1, thus, left side=right side. Therefore, the data is inverted for this memory cell.
Eleventh, when the address of a memory cell is (X, Y)=(2, 2), the conditional equation of left side “(Y address of memory cell+diagonal inversion set value) AND maximum Y address value” is (2+3) AND 3=1, and the conditional equation of right side “(X address of memory cell AND maximum X address value)” is 2 AND 3=2, thus, left side≠right side. Therefore the data is not inverted for the memory cell.
Twelfth, when the address of a memory cell is (X, Y)=(3, 2), the conditional equation of left side “(Y address of memory cell+diagonal inversion set value) AND maximum Y address value” is (2+3) AND 3=1, and the conditional equation of right side “(X address of memory cell AND maximum X address value)” is 3 AND 3=3, thus, left side≠right side. Therefore, the data is not inverted for the memory cell.
Thirteenth, when the address of a memory cell is (X, Y)=(0, 3), the conditional equation of left side “(Y address of memory cell+diagonal inversion set value) AND maximum Y address value” is (3+3) AND 3=2, and the conditional equation of “(X address of memory cell AND maximum X address value)” is 0 AND 3=0, thus, left side≠right side. Therefore, the data is not inverted for the memory cell.
Fourteenth, when the address of a memory cell is (X, Y)=(1, 3), the conditional equation of left side “(Y address of memory cell+diagonal inversion set value) AND maximum Y address value” is (3+3) AND 3=2, and the conditional equation of “(X address of memory cell AND maximum X address value)” is 1 AND 3=1, thus, left side≠right side. Therefore, the data is not inverted for the memory cell.
Fifteenth, when the address of a memory cell is (X, Y)=(2, 3), the conditional equation of left side “(Y address of memory cell+diagonal inversion set value) AND maximum Y address value” is (3+3) AND 3=2, and the conditional equation of right side “(X address of memory cell AND maximum X address value)” is 2 AND 3=2, thus, left side=right side. Therefore, the data is inverted for this memory cell.
Sixteenth, when the address of a memory cell is (X, Y)=(3, 3), the conditional equation of left side “(Y address of memory cell+diagonal inversion set value) AND maximum Y address value” is (3+3) AND 3=2, and the conditional equation of right side “(X address of memory cell AND maximum X address value) is 3 AND 3=3, thus, left side≠right side. Therefore, the data is not inverted for the memory cell.
From the computation results in the foregoing, the left and right side of the computation results match with each other in the fourth, fifth, tenth, and fifteenth computations, resulting in an inversion request signal 110s at the output of the pattern generator PG. As a result of the inversion request signal 110s, the write data for the specific memory cells is inverted as shown by the hatch in FIG. 4. Note that the locations of the specific memory cells are on a diagonal line on the array (diagonal inversion), which is considered effective in evaluating the pattern sensitive faults of a memory device.
As described in the foregoing, the circuit diagram of FIG. 2B is effective in producing a test pattern including a pattern inversion operation. However, in the case where the numbers of memory cells differ in the X and Y directions, there arises a problem that the circuit diagram of FIG. 2B does not always function properly. In other words, certain memory cells are not provided with write data inverted from the neighborhood memory cells in such type of memory device. This discrepancy is described below with reference to FIGS. 5 and 6.
In the example of FIGS. 5 and 6, it is assumed that a diagonal inversion operation will be performed for the uneven numbers of memory cells in X and Y directions, i.e., 8×4 memory cells. In this setting, the maximum X address value is #7, i.e, lower three bits are valid by masking fourth or higher bits. The maximum Y address value is #3, i.e., lower two bits are valid by masking third or higher bits, which is the same as the previous example.
It is also assumed that the X address and Y address both start from 0, and the set value for the diagonal inversion set register 10 is “#3”, which is the same as in the previous example of FIG. 4. The expected memory cell locations that their write data should be inverted are shown by cross marks in FIG. 5. FIG. 6 shows actual memory cell locations resulted from the operation of the circuit diagram of FIG. 2B.
Based on the conditions mentioned above, the process of determining whether the write data for a memory cell defined by the address data should be inverted is described in the following for each and every X, Y address. This process is conducted by computing the right and left of the conditional equation 1 above, and when the computed results match with each other, it is determined that the write data for the address is inverted.
First, the computation results for the addresses from (X, Y)=(0, 0) to (X, Y)=(3, 0) are the same as that described above with reference to FIG. 4, thus, the explanation for these addresses is omitted here.
Second, when the address of a memory cell is (x, Y)=(4, 0), the conditional equation of left side “(Y address of memory cell+diagonal inversion set value) AND maximum Y address value” is (0+3) AND 3=3, and the conditional equation of right side “(X address of memory cell AND maximum X address value)” is 4 AND 7=4, thus, left side≠right side. Therefore, the data is not inverted for the memory cell. Note that since the lower three bits are valid in the right side (X address), “4 AND 7” above is “100 AND 111” which is “100” in binary form, i.e., “4”. Similar rule applies to the following descriptions.
Third, when the address of a memory cell is (X, Y)=(5, 0), the conditional equation of left side “(Y address of memory cell+diagonal inversion set value) AND maximum Y address value” is (0+3) AND 3=3, and the conditional equation of right side “(X address of memory cell AND maximum X address value)” is 5 AND 7=5, thus, left side≠right side. Therefore, the data is not inverted for this memory cell.
Fourth, when the address of a memory cell is (X, Y)=(6, 0), the conditional equation of left side “(Y address of memory cell+diagonal inversion set value) AND maximum Y address value” is (0+3) AND 3=3, and the conditional equation of right side “(X address of memory cell AND maximum X address value)” is 6 AND 7=6, thus, left side≠right side. Therefore, the data is not inverted for the memory cell.
Fifth, when the address of a memory cell is (X, Y)=(7, 0), the conditional equation of left side “(Y address of memory cell+diagonal inversion set value) AND maximum Y address value” is (0+3) AND 3=3, and the conditional equation of right side “(X address of memory cell AND maximum X address value)” is 7 AND 7=7, thus, left side≠right side. Therefore, the data is not inverted for this memory cell.
Sixth, the computation results for the addresses from (X, Y)=(0, 1) to (X, Y)=(3, 1) are the same as that described above with reference to FIG. 4, thus, the explanation for these addresses is omitted here.
Seventh, when the address of a memory cell is (x, Y)=(4, 1), the conditional equation of left side “(Y address of memory cell+diagonal inversion set value) AND maximum Y address value” is (1+3) AND 3=0, and the conditional equation of right side “(X address of memory cell AND maximum X address value)” is 4 AND 7=4, thus, left side≠right side. Therefore, the data is not inverted for the memory cell. As shown in FIG. 5, it is intended that the write data for this memory cell be inverted, which results in discrepancy in the example of FIG. 2B.
Eighth, when the address of a memory cell is (X, Y)=(5, 1), the conditional equation of left side “(Y address of memory cell+diagonal inversion set value) AND maximum Y address value” is (1+3) AND 3=0, and the conditional equation of right side “(X address of memory cell AND maximum X address value)” is 5 AND 7=5, thus, left side≠right side. Therefore, the data is not inverted for this memory cell.
Ninth, when the address of a memory cell is (x, Y)=(6, 1), the conditional equation of left side “(Y address of memory cell+diagonal inversion set value) AND maximum Y address value” is (1+3) AND 3=0, and the conditional equation of right side “(X address of memory cell AND maximum X address value)” is 6 AND 7=6, thus, left side≠right side. Therefore, the data is not inverted for the memory cell.
Tenth, when the address of a memory cell is (x, Y)=(7, 1), the conditional equation of left side “(Y address of memory cell+diagonal inversion set value) AND maximum Y address value” is (1+3) AND 3=0, and the conditional equation of right side “(X address of memory cell AND maximum X address value)” is 7 AND 7=7, thus, left side≠right side. Therefore, the data is not inverted for the memory cell.
Eleventh, the computation results for the addresses from (X, Y)=(0, 2) to (X, Y)=(3, 2) are the same as that described above with reference to FIG. 4, thus, the explanation for these addresses is omitted here.
Twelfth, when the address of a memory cell is (X, Y)=(4, 2), the conditional equation of left side “(Y address of memory cell+diagonal inversion set value) AND maximum Y address value” is (2+3) AND 3=1, and the conditional equation of right side “(X address of memory cell AND maximum X address value)” is 4 AND 7=4, thus, left side≠right side. Therefore, the data is not inverted for the memory cell.
Thirteenth, when the address of a memory cell is (X, Y)=(5, 2), the conditional equation of left side “(Y address of memory cell+diagonal inversion set value) AND maximum Y address value” is (2+3) AND 3=1, and the conditional equation of right side “(X address of memory cell+maximum X address value)” is 5 AND 7=5, thus, left side≠right side. Therefore, the data is not inverted for the memory cell. However, as shown in FIG. 5, it is intended that the write data for this memory cell be inverted, which results in discrepancy in the example of FIG. 2B.
Fourteenth, when the address of a memory cell is (X, Y)=(6, 2), the conditional equation of left side “(Y address of memory cell+diagonal inversion set value) AND maximum Y address value” is (2+3) AND 3=1, and the conditional equation of right side “(X address of memory cell AND maximum X address value)” is 6 AND 7=6, thus, left side≠right side. Therefore, the data is not inverted for the memory cell.
Fifteenth, when the address of a memory cell is (X, Y)=(7, 2), the conditional equation of left side “(Y address of memory cell+diagonal inversion set value) AND maximum Y address value” is (2+3) AND 3=1, and the conditional equation of right side “(X address of memory cell AND maximum X address value)” is 7AND 7=7, thus, left side≠right side. Therefore, the data is not inverted for the memory cell.
Sixteenth, the computation results for the addresses from (X, Y)=(0, 3) to (X, Y)=(3, 3) are the same as that described above with reference to FIG. 4, thus, the explanation for these addresses is omitted here.
Seventeenth, when the address of a memory cell is (X, Y)=(4, 3), the conditional equation of left side “(Y address of memory cell+diagonal inversion set value) AND maximum Y address value” is (3+3) AND 3=2, and the conditional equation of right side “(X address of memory cell AND maximum X address value)” is 4 AND7=4, thus, left side≠right side. Therefore, the data is not inverted for the memory cell.
Eighteenth, when the address of a memory cell is (X, Y)=(5, 3), the conditional equation of left side “(Y address of memory cell+diagonal inversion set value) AND maximum Y address value” is (3+3) AND 3=2, and the conditional equation of right side “(x address of memory cell+maximum X address value)” is 5 AND 7=5, thus, left side≠right side. Therefore, the data is not inverted for the memory cell.
Nineteenth, when the address of a memory cell is (X, Y)=(6, 3), the conditional equation of left side “(Y address of memory cell+diagonal inversion set value) AND maximum Y address value” is (3 +3) AND 3=2, and the conditional equation of right side “(X address of memory cell+maximum X address value)” is 6 AND 7=6, thus, left side≠right side. Therefore, the data is not inverted for this memory cell. However, as shown in FIG. 5, it is intended that the write data for this memory cell be inverted, which results in discrepancy in the example of FIG. 2B.
Twentieth, when the address of a memory cell is (X, Y)=(7, 3), the conditional equation of left side “(Y address of memory cell+diagonal inversion set value) AND maximum Y address value” is (3+3) AND 3=2, and the conditional equation of right side “(X address of memory cell AND maximum X address value)” is 7 AND 7=7, thus, left side≠right side. Therefore, the data is not inverted for this memory cell.
From the above explained computation results, it is seen that an inversion request signal 110s is not produced due to the mismatch of the left and right side of the equation in the results at fifth, seventh, thirteenth, and nineteenth computations. Therefore, it is obvious that an appropriate inversion operation is not available at the four intended memory locations as shown in FIG. 6. Thus, in the case where the memory device under test has an array of memory cells with different number of cells between the X and Y directions, there arises a problem that the diagonal inversion will not function properly.
To attain the inversion operation for all of the intended locations of the memory cells, it is necessary to produce a complicated test program, which requires a considerable amount of time and work. Further, because such an approach of using a test program makes it impossible of continuously and automatically reading and writing the memory device under test, test throughput is substantially decreased, resulting in increase in the cost of memory devices.